The present invention relates to a semiconductor integrated circuit, and particularly to a technology for electrically cutting off a logic circuit unit from operating power supplies therefor upon standby and reducing a leak current developed upon standby. The present invention relates to a technology effective for application to, for example, a battery-driven cellular phone or PAD (Personal Digital Assistant) or the like.
With technical advances in semiconductor integrated circuit and the wide range of its application field, a reduction in power consumption of the semiconductor integrated circuit (semiconductor chip) has become important in recent years. Namely, the reduction in power consumption of the semiconductor integrated circuit has come to be an important consideration in battery-driven applications such as a PDA, etc., in maximizing operating time. Reducing the power-supply or source voltage is most effective for the reduction in power consumption. However, as side effects may be mentioned, a reduction in current supply capability of each transistor, and a reduction in working speed of the transistor can result. In order to overcome such a problem, there is known a method of reducing Vth (threshold voltage) of the transistor. However, the mere reduction in threshold voltage will increase the leak current developed when the transistor is held in an off state. In doing so, needless current consumption will increase even when the semiconductor integrated circuit is brought to a standby state. The standby state is a so-called one low power consumption mode capable of stopping the supply of a clock signal for synchronous operation, for example and achieving its state. A technology that has been proposed to overcome such a problem is the MT-CMOS (Multi-Threshold CMOS). The present technology has been described in, for example, xe2x80x9cElectronic Technologyxe2x80x9d issued by THE NIKKAN GOGYO SHINBUN, LTD., p.29-32, September 1994.
The MT-CMOS technology utilizes transistors (high threshold voltage transistors) each having a large threshold voltage ranging from about 0.5V to about 0.7V and transistors (low threshold transistors) each having a small threshold voltage ranging from about 0.2V to about 0.3V when an operating power supply is about 1V, for example. Low threshold voltage transistors are used for logic gates constituting a logic circuit group. Operating power supplies for the respective logic gates are supplied from source or power-supply terminals through MOS transistors for power supply, which comprise the high threshold voltage transistors. When the MOS transistors are turned on to supply the operating power supplies to each individual logic gate, the low threshold voltage MOS transistors constituting the logic gates can be operated at high speed because of their low threshold voltages. When the MOS transistors are turned off upon standby, a leak current that will flow through a turnedoff transistor of each logic gate, can be cut off because of the high threshold voltage of each MOS transistor for power supply.
It has been revealed by the present inventors that in the MT-CMOS technology, the leak current developed upon standby can be reduced, whereas the leak current developed upon operation cannot be reduced in spite of the operating clock frequency.
Namely, most personal digital assistants respectively have an operation mode between a high-speed operation mode high at the clock signal frequency and a standby mode for stopping a clock signal, i.e., a low-speed operation mode operated at a low-speed clock signal frequency. During a waiting operation of a cellular phone, for example, call detection and an outgoing or dialing operation for notifying the present position may be carried out at predetermined intervals, and less throughput is provided as compared with signal processing or the like made while a call is in progress. Thus, such a waiting process will be enough if the phone is operated in synchronism with a low-speed clock signal.
A circuit operated in synchronism with the clock signal performs a logic operation for each clock signal cycle and carries out the operation of latching the result thereof in a signal transmission system. If the clock signal becomes slow, then the logic operation is determined by some of the clock cycle, and the circuit is kept at a constant state during the remaining period. At this time, each turned-off transistor continues to have a flow of leak current if the threshold voltage thereof is small. The MT-CMOS technology is accompanied by a problem that since the high threshold voltage MOS transistors for supplying power remain at the on state except for during the standby state, the leak current relatively increased when the frequency of the operating clock signal for each logic gate is low, cannot be reduced.
An object of the present invention is to reduce the leak current developed when a transistor is held in an off state.
Another object of the present invention is to provide a data processor with a semiconductor integrated circuit capable of reducing the leak current developed in a turned-off transistor when the frequency of the operating clock signal is low, in other words, when a logic circuit block is operated at low speed.
A further object of the present invention is to provide a data processor with a semiconductor integrated circuit wherein operating power supplies are supplied to within each of the logic circuit blocks through a switch transistor whose threshold voltage is rendered high as compared with each transistor lying in the logic circuit block, and a leak current flowing through each turned-off transistor lying within the logic circuit block can be reduced.
The above and other objects, and novel features of the present invention will become apparent from the following description of the present specification and the accompanying drawings.
The present invention includes a logic circuit block operated in synchronism with a clock signal, at least one power supply switch which supplies power to the logic circuit block, and a switch control circuit which controls the power supply switch. The switch control circuit switch-controls the power supply switch so as to bring a period shorter than the cycle of the clock signal to the on operation period in synchronism with the clock signal. As an example, using the above, the logic circuit block is activated in synchronism with a first operating clock signal having a frequency lower than that of a second operating clock signal for defining the maximum operation speed of the logic circuit block. At this time, the logic circuit block does not develop a malfunction in the logic operation itself theoretically if capable of operation for each cycle of the first operating clock signal at least only for a predetermined time defined by the frequency of the second operating clock signal, for example, a one-cycle period. This is because the logic block is designed so as to operate based on the second operating clock signal. Thus, since the supply of operating power to the logic circuit block is cut off except for a period necessary for a circuit operation, a leak current that will flow through each turned-off transistor in the logic circuit block in the meantime, can be significantly reduced.
If consideration is given to points about a high-speed operation of the logic circuit block with respect to reductions in the operating power supplies and a reduction in leak current at standby in a manner similar to the MT-CMOS technology at this time, then threshold voltages of transistors constituting the logic circuit block can be rendered relatively small to allow the high-speed operation upon a low-voltage operation. Further, the threshold voltage of a current supply switch can be rendered relatively large to reduce the leak current at standby.
When the above means of the present invention is compared with the MT-CMOS technology, the present invention can reduce the leak current developed when the transistors of the logic circuit block are turned off upon low-speed operation synchronized with a low-frequency clock signal which does not allow for the MT-CMOS technology. However, the logic circuit block is not limited to a CMOS circuit in the present invention. Further, the operating power supply is not limited to a low voltage like 1V. Furthermore, the threshold voltages of the power supply switch and the transistors constituting the logic circuit block are not limited to the above relation. Imposing such a limitation on the present invention is most suitable in terms of low power consumption of a low-voltage operated semiconductor integrated circuit intended or planned for high-speed operation.
Further, the above means of the present invention is compared with VT-CMOS (Variable Threshold-CMOS) technology. The VT-CMOS technology aims to change a substrate bias voltage to thereby control the threshold voltage of each MOS transistor. A substrate bias voltage of a logic circuit block is controlled to increase the threshold voltage upon standby operation, for example. Thus, the leak current flowing through each MOS transistor turned off upon standby can be reduced. In the VT-CMOS technology, relatively large capacitive components parasitic on a substrate or well shared between many MOS transistors must be charged or discharged, and a relatively long time interval is required to change the threshold voltage. Namely, it is not possible to change the potential applied to the substrate or well at high speed. Thus, even when the logic circuit block is activated in synchronism with a low-frequency clock signal, it is difficult to perform switching to the substrate bias voltage for each clock signal cycle. Further, an improvement in drive capability of an output transistor of a voltage generating circuit, which performs a change in substrate or well potential, and the provision of plural voltage generating circuits are also considered to allow the change in potential applied to the substrate or well. Since, however, an occupied area is required in terms of layout, this is not considered to be realistic.
Setting means for programmably setting the on operation period of the power supply switch is provided. The switch control circuit can be configured so as to determine the on operation period, based on a set value supplied from the setting means. Thus, the reduction in leak current can be controlled to the maximum according to the clock signal frequency to be used.
Control on the on operation period for the power supply switch can be carried out only when a specific operation mode like a first operation mode is established. The power supply switch can always be turned on in another operation mode like a second operation mode. Further, the semiconductor integrated circuit may not have another operation mode like the second operation mode.
The first and second operation modes can be defined as operation modes for determining the frequency of a clock signal. A clock control circuit is provided which is supplied with, for example, a first clock signal and a second clock signal higher than the first clock signal in frequency. The clock control circuit supplies the first clock signal to the logic circuit block when the first operation mode is specified, and supplies the second clock signal to the logic circuit block when the second operation mode is specified. Thus, when the first operation mode in which the logic circuit block is activated at low speed, is designated, the leak current flowing through each transistor can be reduced within the logic circuit block as described above.
The logic circuit block can be configured inclusive of at least one combinational circuit and at least one sequence circuit activated in synchronism with a clock signal. The size of a logic scale thereof is out of the question. The sequence circuit is configured as a flipflop or a latch circuit or the like.
When, for example, the sequence circuit is operated so as to capture and hold data supplied to a data input terminal of the sequence circuit in synchronism with a first edge of a clock signal supplied to a clock terminal of the sequence circuit, the switch control circuit can be configured inclusive of detecting means which detects the first edge of the first clock signal, a counter which counts the second clock signal and is reset based on a detected signal of the first edge, a comparator which detects a coincidence between a count of the counter and the set value, and a signal generating circuit which generates a signal for determining the on operation period of the power supply switch, based on the first edge of the first clock signal and the coincident detection obtained by the comparator.
When consideration is given to the case in which the semiconductor integrated circuit supports a standby mode defined as a low power consumption mode, the clock control circuit can be configured so as to stop the supply of a clock signal to the logic circuit block when a third operation mode is specified. The power supply switch may always be kept in an off state in response to this third mode. Alternatively, the switch control circuit may bring the power supply switch to an on operation for each predetermined period in,response to the designation of the third mode to refresh each internal node of the logic circuit block. If no refresh operation is taken, then an electrical charge at the node leaks to a substrate or the like and is gradually reduced in a state in which the supply of the electrical charge through the power supply switch is completely cut off. The refresh operation aims to make up for such a reduction.
The power supply switch can be defined as either a first switch connected to a power-supply or source terminal on the high-potential side or a second switch connected to a power-supply or source terminal on the low-potential side, or both switches. When both are defined as objects to be controlled, the time required to return the power from its cut-off state to its supply state can be shortened.
A data processing system or equipment of the present invention according to another aspect includes a plurality of logic circuit blocks operated in synchronism with a clock signal supplied thereto, a clock control circuit which controls the supply of the clock signal to the plurality of logic circuit blocks, at least one power supply switch which controls the supply of a power supply or source to the plurality of logic circuit blocks, and a switch control circuit which controls the turning on and off of the power supply switch. The clock control circuit supplies a first clock signal to the plurality of logic circuit blocks in response to the designation of a lowspeed mode, supplies a second clock signal higher than the first clock signal in frequency to the plurality of logic circuit blocks in response to the designation of a high-speed mode, and stops the supply of the clock signal to a predetermined logic circuit block in the plurality of logic blocks in response to the designation of a standby mode. Further, the switch control circuit switchcontrols the power supply switch in response to the designation of the low-speed mode so as to bring a period shorter than the cycle of the first clock signal to an on operation period in synchronism with the first clock signal, bring the power supply switch to a continuous on state in response to the designation of the high-speed mode, and bring the power supply switch of the predetermined logic block to a continuous off state in response to the designation of the standby mode.
A data processing system or equipment of the present invention according to a further aspect includes a plurality of logic circuit blocks operated in synchronism with a clock signal supplied thereto, a clock control circuit which controls the supply of the clock signal to the plurality of logic circuit blocks, at least one power supply switch which controls the supply of a power supply to the plurality of logic circuit blocks, and a switch control circuit which controls the turning on and off of the power supply switch. The clock control circuit supplies a first clock signal to the plurality of logic circuit blocks in response to the designation of a low-speed mode, supplies a second clock signal higher than the first clock signal in frequency to the plurality of logic circuit blocks in response to the designation of a high-speed mode, and stops the supply of the clock signal to a predetermined logic circuit block of the plurality of logic blocks in response to the designation of a standby mode. The switch control circuit switch-controls the power supply switch in response to the designation of the low-speed mode so as to bring a period shorter than the cycle of the first clock signal to an on operation period in synchronism with the first clock signal, bring the power supply switch to a continuous on state in response to the designation of the high-speed mode, and turn on the power supply switch for each predetermined period in response to the designation of the standby mode, thereby refreshing internal nodes in the logic circuit blocks.
The plurality of logic circuit blocks can be defined as a CPU subjected to clock control and power supply control responsive to the high-speed, low-speed and standby modes, an interrupt control circuit subjected to the clock control and power-supply control responsive to the high-speed and the low-speed, etc. The data processing system including those logic circuit blocks can constitute a multi-chip or single-chip processor.
The power control circuit can resume the supplying of power to the logic circuit blocks in response to a standby mode reset signal, and the clock control circuit can resume the supplying of a clock signal to the logic circuit blocks in response to the standby mode reset signal.
Display means, input means and communication means placed under the control of the processor can further be provided to constitute a data processing system such as for a PDA. In the data processing system, the processor is capable of performing signal processing and protocol processing at high speed in a communication state made by the communication means, for example. In a waiting state of the communication means, an incoming-call decision, etc. may be performed at low speed. Upon such a low-speed operation, the leak current can be reduced and the battery operating time can be extended.